Signal State Dynamics: Dominant vs. Recessive Logic

In this technical deep dive, we move beyond simple binary 1s and 0s to examine the electrical behavior of the bus. In CAN protocol, logic is determined by differential voltage. We define "Dominant" (logic 0) and "Recessive" (logic 1) states, which are the fundamental building blocks of bus arbitration. You will learn how the "wired-AND" logic allows the bus to resolve conflicts when two ECUs attempt to transmit simultaneously.

We will perform simulations of shorted CAN lines—a critical skill for both vehicle diagnostics and forensic recovery. What happens when CAN-H is shorted to ground? How does the system react to a "Bus Off" state? Understanding these failure modes is essential for a digital forensics investigator who may be working with damaged vehicles or tampered wiring. We will use simulation tools to visualize these states, ensuring you can recognize an unhealthy bus signal before you even attempt to connect your logic analyzer or ESP32-based sniffing hardware.